1. Technical Field
The present disclosure relates to a semiconductor memory device and, more particularly, a bit-line equalizer capable of varying the width of an equalizing transistor irrespective of a memory cell pitch, a semiconductor memory device including the bit-line equalizer, and a method for manufacturing the bit-line equalizer.
2. Discussion of Related Art
A semiconductor memory device such as a dynamic random access memory (DRAM) includes a plurality of memory cell arrays each having a plurality of memory cells storing data and a plurality of sense amplifiers sensing and amplifying the data stored in the memory cells. The plurality of memory cell arrays and the plurality of sense amplifiers are alternately arranged. Each of the sense amplifiers is connected to a bit-line and an inverted bit-line, senses data signals on the bit-line and the inverted bit-line, and amplifies the sensed data signals. The operation of sensing and amplifying the data signals will be explained in detail.
The bit-line and the inverted bit-line are precharged with a predetermined bit-line voltage before a wordline is enabled. When the wordline is enabled, a cell transistor of a memory cell is turned on and charge-sharing occurs between a cell capacitor of the memory cell and the bit-line, so that a data signal corresponding to data stored in the memory cell is applied to the bit-line.
The sense amplifier senses a difference between the bit-line voltage of the precharged inverted bit-line and the data signal of the bit line and amplifies the difference to read the data stored in the memory cell. Here, the difference is a small value and, thus, it is necessary to precharge the bit-line and the inverted bit-line with the same bit-line voltage and to maintain the bit-line voltage. For this operation, the sense amplifiers include a bit-line equalizer.
FIG. 1 is a circuit diagram of a conventional bit-line equalizer 100. While the bit-line equalizer is included in a semiconductor memory device employing an open bit-line structure in FIG. 1, it will be understood by those of ordinary skill in the art that the bit-line equalizer illustrated in FIG. 1 can be included in semiconductor memory devices using other bit-line structures.
The bit-line equalizer 100 includes a plurality of sub-equalizers EQ0, EQ2, . . . respectively corresponding to bit-line pairs respectively composed of bit-lines BL0, BL2, . . . and inverted bit-lines /BL0, /BL2, . . . . Each of the sub-equalizers EQ0, EQ2, . . . includes three MOS transistors N1, N2 and N3 controlled in response to an equalization enable signal EQ_CTRL. The sub-equalizers EQ0, EQ2, . . . form an equalizer EQ.
Specifically, the sub-equalizer EQ0 includes precharge transistors N1 and N2 and an equalizing transistor N3. The precharge transistors N1 and N2 precharge the bit-line BL0 and the inverted bit-line /BL0 with a bit-line voltage VBL in response to the equalization enable signal. The equalizing transistor N3 equalizes the bit-line BL0 and the inverted bit-line /BL0 in response to the equalization enable signal such that both the bit-line BL0 and the inverted bit-line /BL0 are maintained at the bit-line voltage VBL.
FIG, 2 is a layout of a bit-line equalizer 200 showing more bit lines than the equalizer 100 illustrated in FIG. 1. In FIG. 2, the right part is a memory cell array area MEM_AREA and the left part is a sensing and amplification area SA_AREA.
Referring to FIG, 2, the bit-line equalizer 200 includes a transistor active region ACTIVE_TR, a polysilicon gate GP formed on the active region ACTIVE_TR, bit-line pairs BL0 and /BL0, BL2 and /BL2, . . . , a plurality of contact holes for connecting the bit-line pairs BL0 and /BL0, BL2 and /BL2, . . . to the active region ACTIVE_TR, and a plurality of contact holes for supplying the bit-line voltage VBL to the active region ACTIVE_TR.
As illustrated in FIG. 1, the equalizing transistor N3 that equalizes the bit-line BL0 and the inverted bit-line /BL0 is arranged between the bit-line BL0 and the inverted bit-line /BL0. Accordingly, the width of the equalizing transistor N3 depends on a cell pitch, that is, the distance between the bit-line BL0 and the inverted bit-line /BL0, irrespective of the size of the sense amplifier including the bit-line equalizer 200.
With the development of improved performance of a semiconductor memory device, the operating speed of the semiconductor memory device is increased and, thus, it is necessary to reduce an equalizing time between a bit-line and an inverted bit-line. Furthermore, as the capacity of the semiconductor memory device increases, a memory cell size, that is, a cell pitch, of the semiconductor memory device decreases.
To reduce the equalizing time, the width of the equalizing transistor N3 has to be increased, however, the cell pitch is fixed. Thus, the equalizing time cannot be decreased when the layout illustrated in FIG. 2 is used.
Moreover, a parasitic transistor PATR, two of which are shown in FIG. 1, is formed between neighboring bit-lines BL0 and BL2, /BL0 and /BL2, BL2 and BL4, /BL2 and /BL4, . . . when the layout illustrated in FIG. 2 is used. Each parasitic transistor PATR causes current leakage,